system-administration

Bosch Group

<div><section><div><p></p><h2>Company Description</h2></div><div><p><strong>At Bosch, we shape the future by inventing high-quality technologies and services that spark enthusiasm and enrich people’s lives. Our promise to our associates is rock-solid: we grow together, we enjoy our work, and we inspire each other. </strong><strong>Join in and feel the difference.</strong></p><p>The Robert Bosch GmbH<em> </em>is looking forward to your application!</p></div></section><section><div><p></p><h2>Job Description</h2></div><div><p>SRAM-based Compute-in-Memory (CIM) presents new paradigm in microcontroller subsystem design. RISC-V allows parametrization to enable pre-processing and AI workloads such as filter banks, directional microphones, or recurrent networks, in combination with acceleration offered by SRAM CIM. In this thesis, the interaction between RISC-V cluster and SRAM-based CIM will be evaluated, including interconnect topologies and CIM partitioning. Fast model will be first developed to accelerate the exploration and evaluation of such system, prior to RTL implementation.</p><ul><li>During your thesis, you will evaluate SRAM-based CIM hardware accelerators for DSP and AI workloads.</li><li>You will develop a fast model RISC-V based subsystem.</li><li>Furthermore, you will also integrate these hardware accelerator models into the FAST model.</li><li>Additionally, you will analyse the performance metrics of the subsystem and optimise the components.</li><li>You will also instantiate an SoC template to implement this subsystem and validate its functionality.</li><li>Last but not least, you will gain experience and collaborate in a cross-functional team spanning algorithm, deployment, and hardware.</li></ul></div></section><section><div><p></p><h2>Qualifications</h2></div><div><ul><li><strong>Education: </strong>Master studies in the field of Electrical Engineering, Computer Science or comparable</li><li><strong>Experience and Knowledge:</strong> in Digital Systems, Computer Architecture, RTL Design (VHDL/SystemVerilog) Python, as well as in Linux and LaTeX; background knowledge in Neural Networks</li><li><strong>Personality and Working Practice:</strong> independent, reliable and motivated</li><li><strong>Languages: </strong>very good in English</li></ul></div></section><section><div><p></p><h2>Additional Information</h2></div><div><p><strong>Start:</strong> according to prior agreement<br> <strong>Duration:</strong> 6 months</p><p>Requirement for this thesis is the enrollment at university. Please attach your CV, transcript of records, examination regulations and if indicated a valid work and residence permit.</p><p>Diversity and inclusion are not just trends for us but are firmly anchored in our corporate culture. Therefore, we welcome all applications, regardless of gender, age, disability, religion, ethnic origin or sexual identity.</p><p><strong>Need further information about the job?</strong><br> Ahmet Erozan (Functional Department)<br> +49 711 811 32710</p><p>#LI-DNI</p></div></section></div>

Master Thesis in Design and Evaluation of SRAM-based Compute-In-Memory in RISC-V based Subsystem